THE NEON CENTRAL PROCESSING UNIT
Copyright 1996 Lewdum Inc.
Chapter 1 Architecture
Chapter 2 Conditional Execution
Chapter 3 Instruction Set
Appendix A Common Interrupts
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CHAPTER 1 Architecture
A, B
General purpose 8-bit registers. Also known as "accumulators."
PC
16-bit program counter. The CPU fetches the next instruction from RAM[PC].
SP
TODO
CND
The condition flag, used for conditional execution (see Chapter 2).
RAM
64 KB (65,536 bytes) of byte-addressable, random-access memory.
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CHAPTER 2 Conditional Execution
TODO
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CHAPTER 3 Instruction Set
This chapter lists and describes every instruction the Neon CPU supports.
Representation
Each instruction is accompanied by a description of its basic operation and its
"quirks," if any. When the instruction is non-trivial (i.e. it does something),
this description may also contain a pseudo-code equivalent of its operation.
Instructions are represented by 3-letter mnemonics. Of course, the CPU itself
never sees the mnemonics, but they are used by the official Neon Assembler. On
the right side of the page, an expansion of the mnemonic is included.
Arguments
Most instructions take arguments, that is, data immediately adjacent to them in
the compiled binary which their operation depends upon. This data may be of
several types, represented here by single letters:
b an 8-bit literal byte
w a wide (16-bit) literal (possibly an address)
Additionally, the symbol x stands for either accumulator (A or B).
Listing
NOP No OPeration
Does nothing.
LxI b Load x with Immediate
Sets register x to the immediate byte b.
x <- b
LxM w Load x with Memory
Sets register x to the byte stored at memory address w.
x <- RAM[w]
Lxy Load x with y
Sets register x to register y.
LAA and LBB are not valid instructions.
x <- y
STx w STore x
Stores register x into memory address w.
RAM[w] <- x
ADI b ADd Immediate
Adds the immediate byte b to register A.
A <- A + b
ADM w ADd Memory
Adds the byte stored at memory address w to register A.
A <- A + RAM[w]
ADx ADd x
Adds register x to register A.
ADA is not a valid instruction.
A <- A + x
SBI b SuBtract Immediate
Subtracts the immediate byte b from register A.
A <- A - b
SBM w SuBtract Memory
Subtracts the byte stored at memory address w from register A.
A <- A - RAM[w]
SBx SuBtract x
Subtracts register x from register A.
SBA is not a valid instruction.
A <- A - x
TEI b Test EQual to Immediate
Sets CND to the result of the operation A = b.
CND <- A = b
TEM w Test EQual to Memory
Sets CND to the result of the operation A = m, where m is the byte stored at
memory address w.
CND <- A = RAM[w]
TEx Test EQual to x
Sets CND to the result of the operation A = x.
TEA is not a valid instruction.
CND <- A = x
TGI b Test Greater than Immediate
Sets CND to the result of the operation A > b.
CND <- A > b
TGM w Test Greater than Memory
Sets CND to the result of the operation A > m, where m is the byte stored at
memory address w.
CND <- A > RAM[w]
TGx Test Greater than x
Sets CND to the result of the operation A > x.
TGA is not a valid instruction.
CND <- A > x
TLI b Test Less than Immediate
Sets CND to the result of the operation A < b.
CND <- A < b
TLM w Test Less than Memory
Sets CND to the result of the operation A < m, where m is the byte stored at
memory address w.
CND <- A < RAM[w]
TLx Test Less than x
Sets CND to the result of the operation A < x.
TLA is not a valid instruction.
CND <- A < x
JMP w JuMP
Sets PC to the immediate 16-bit address w. Also known as the "absolute
jump."
PC <- w
JRF b Jump Relative Forwards
Adds the immediate byte b to PC. TODO Counts from...
PC <- PC + b
JRB b Jump Relative Backwards
Subtracts the immediate byte b from PC. TODO Counts from...
PC <- PC - b
INT b INTerrupt
Calls the vendor-defined interrupt service routine (ISR) with code b. For
technical reasons, interrupt code 0 is hardcoded to do nothing. Therefore,
the instruction INT 0 is equivalent to NOP, except in that it wastes more
space.
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APPENDIX w Common Interrupts
Although, as mentioned in Chapter 3, interrupt codes are vendor-defined, some
are so commonly implemented that they may be said to be "quasi-standardized."
Such interrupts are the topic of this appendix.
Input/Output
INT 1
Prints register A to the console, followed by a line break. This
interrupt only makes sense in a development environment where a terminal is
connected to the CPU. Otherwise, it does nothing.
INT 2
Same as INT 1, but prints B instead.
INT 3
Same as INT 1, but prints the ASCII character encoded by A and does NOT
follow it with a line break. Meant to be used for printing dynamically
generated strings. See the String Operations section to print constant
strings stored in RAM.
Vector Operations
INT 0x30 Decimal 48
TODO
String Operations
INT 0x50 Decimal 80
Prints an ASCII string stored in RAM. Much faster than INT 3 for multi-
character strings. TODO
Miscellaneous
INT 0xFF Decimal 255
Halts the CPU. Note that, in many environments, the CPU is supposed to never
halt, and this interrupt will have no effect. w common way to force the CPU
to idle whether it supports INT 0xFF or not is to enter an infinite loop
immediately after calling the interrupt:
INT 0xFF
JRB 0